1. Field of the Invention
The present invention relates to a high-aspect ratio contact in a semiconductor device and a method of forming the same. In particular, the present invention relates to formation of a contact in a semiconductor device with a refractory metal and a refractory metal nitride liner that assists in filling of a contact hole in which the contact is situated. More particularly, the present invention relates to an aluminum or aluminum alloy-filled contact plug that fills a contact hole in a semiconductor device that is lined with a titanium layer and at least one titanium nitride layer. The titanium and the first of the at least one titanium nitride layers are formed by chemical vapor deposition. Subsequently formed titanium nitride layers, if any, are formed by physical vapor deposition (PVD).
2. Background Technology
In the microelectronics industry, a substrate refers to one or more semiconductor layers or structures that include active or operable portions of semiconductor devices. In the context of this document, the term “semiconductor substrate” is defined to mean any construction comprising semiconductive material, including, but not limited to, bulk semiconductive material such as a semiconductive wafer, either alone or in assemblies comprising other materials thereon, and semiconductive material layers, either alone or in assemblies comprising other materials. The term “substrate ” refers to any supporting structure including, but not limited to, the semiconductive substrates described above.
In the fabrication of semiconductor devices, metal contacts are formed over semiconductor substrates that have been processed to form devices connected to each other to form integrated circuits. In particular, aluminum and aluminum alloy lines have been deposited into vias and other recesses such as trenches and contact corridors. This method of metallization is used generally in the microelectronics industry. However, as devices have been miniaturized due to requirements for a higher device density on a semiconductor substrate and a smaller device, the recesses to be filled have higher aspect ratios, where an aspect ratio is the depth of the recess divided by the width thereof.
One need for higher aspect ratio recesses is the formation of deeper contacts where, for example, a stacked capacitor for a dynamic random access memory (DRAM) is formed and then covered over by a dielectric layer. For such a stacked DRAM capacitor, a contact with an aspect ratio greater than 5:1 would need to be formed in two steps using known prior art processes. Such prior art processing produces a conductive structure having two interconnect halves with a physical seam therebetween. Typically, the two interconnect halves have a width or cross-sectional footprint of about 0.35 microns or smaller. Alignment of the small footprint interconnect halves is problematic at best, and fabrication yield with such a process prerequisite is undesirable. Also undesirable is an increased resistivity caused by the physical seam between the two interconnect halves.
Difficulties have been encountered in depositing aluminum lines and contacts by conventional sputtering processes when submicron high-aspect ratio recesses are to be filled. As a recess is made smaller and deeper (i.e., higher aspect ratio), the bottom and sides of the recess will receive less sputtered target material than the opening to the recess. Additional sputtering will result in a detrimental phenomena known as bread loafing where a layer of sputtered target material closes off the opening to the recess. Thus over time, the bottom and sides of the recess receive inadequate amounts of the sputtered metal material and the sputtered metal material overhangs and closes over the opening to the recess before the recess is substantially filled.
While the aluminum and the silicon in the semiconductor substrate must be electrically connected, it has become useful to use intermediate layers to provide better electrical connection to the silicon and to provide a metallurgical barrier between silicon and aluminum to prevent spiking of the aluminum into the silicon. Spiking can interfere with the performance and reliability of the integrated circuit. Conventionally, one method which has been used to accomplish the metallurgical barrier has been to form a layer of titanium over a semiconductor substrate at the interconnect-exposed site. Titanium silicide is then formed at the interconnect-exposed site and a titanium nitride layer is formed elsewhere, in that the titanium layer is exposed to a nitrogen atmosphere. While this method forms a metallurgical barrier between silicon and aluminum to prevent spiking, it often is inadequate to form the titanium nitride barrier because of the competing simultaneous formation of titanium silicide and titanium nitride at the titanium region that covers the exposed semiconductor substrate site.
One prior art solution to this inadequate prior art method has been to form the titanium silicide barrier layer first and then to sputter additional titanium nitride over the titanium silicide or titanium silicide/titanium nitride layer. In this way, a sufficient thickness of titanium nitride may be formed to provide a desired thickness in a barrier layer.
As stated, sputtered layers of titanium nitride have been used in integrated circuits as barrier layers for recesses, such as contact holes, vias, and interconnects. Sputter deposited titanium nitride, however, is not very conformal and its step coverage within high-aspect ratio recesses is poor. As such, there results an unacceptably thin or discontinuous titanium nitride barrier layer for a high-aspect ratio recess.
As aspect ratios have been increasing for recesses in microelectronic devices, the need for substantial recess filling with sputtered aluminum and aluminum alloy metallization material has proved inadequate in spite of improved titanium nitride barrier layers. While high pressure and/or high temperature aluminum reflow recess filling techniques have been developed, a substantially filled recess having an aspect ratio exceeding 5:1 has been difficult or impractical to achieve.
It has been proposed to form a titanium nitride layer in the recess by chemical vapor deposition (CVD), for example, by using titanium tetrachloride (TiCl4) in the presence of NH3, H2, and Ar. Although the TiCl4 CVD process has improved reflow techniques, substantially filled recesses with aspect ratios greater than about 5:1 have been elusive. One problem that has been experienced is that aluminum reflow requires a substantially pristine refractory metal nitride surface, whereas interstitial titanium nitride layer impurities incident to the TiCl4 CVD process have caused the aluminum to become impure. As a result, aluminum loses its relatively low-friction flowing or sliding ability over the impure titanium nitride layer.
Methods have been proposed to drive the interstitial impurities out of the titanium nitride layer by using thermal energy, but the thermal limit or budget of the fabrication process must be monitored so as avoid a yield decrease. Additionally, it has been observed that a thermal cleansing of the titanium nitride layer leaves significant voids in the titanium nitride layer that also resists flow of the aluminum thereacross. Attempts have been made to “stuff” the interstices in the titanium nitride layer with nitrogen. Even with a stuffing technique, however, substantially filled recesses with aspect ratios that exceed 5:1 are not readily realized.
What is needed is a method of lining and substantially filling a high-aspect ratio recess with aluminum metallization or equivalents in microelectronic device fabrication where the aspect ratio of the recess exceeds 5:1. What is also needed is a method of forming a high-aspect ratio structure that allows for a taller microelectronic component, such as a taller stacked DRAM capacitor, where the interconnect to the stacked DRAM capacitor is unitary and formed by a single recess filling process.